Hardware Layer
IB Syllabus: A1.1 — Computer hardware and operation, A1.2.3–A1.2.5 — Logic gates and Boolean algebra
Table of Contents
Overview
The Hardware Layer covers the physical components that make computing possible — from the logic gates that form the foundation of all digital circuits, through the CPU and memory hierarchy, to cloud infrastructure. Understanding hardware is essential for appreciating how software instructions become physical operations.
This layer covers all 9 outcomes of A1.1 (Computer hardware and operation) plus A1.2.3–A1.2.5 (Logic gates and Boolean algebra). Where topics connect to the Operating Systems layer (A1.3), cross-references are provided.
Sub-pages
| # | Topic | Syllabus | Key Concepts | Level |
|---|---|---|---|---|
| 1 | Logic Gates | A1.2.3, A1.2.4, A1.2.5 | 7 gates, truth tables, K-maps, Boolean algebra, logic diagrams | SL + HL |
| 2 | CPU Architecture | A1.1.1, A1.1.5, A1.1.6(HL) | ALU, CU, registers, FDE cycle, buses, pipelining (HL) | SL + HL |
| 3 | GPU | A1.1.2, A1.1.3(HL) | Parallel processing, real-world applications, CPU vs GPU (HL) | SL + HL |
| 4 | Primary Memory | A1.1.4 | Memory hierarchy, RAM, ROM, cache (L1/L2/L3), cache hit/miss | SL + HL |
| 5 | Secondary Storage | A1.1.7 | SSD, HDD, optical, flash, NAS — speed/capacity/cost tradeoffs | SL + HL |
| 6 | Compression | A1.1.8 | Lossy vs lossless, RLE, transform coding (DCT) | SL + HL |
| 7 | Cloud Computing | A1.1.9, A1.3.2 | SaaS, PaaS, IaaS, virtualization | SL + HL |
Teaching Sequence
These topics follow the classroom teaching order (W8–W15), starting with logic gates as the foundation for understanding how CPUs work:
- Logic Gates (W8–W10) — Boolean algebra and circuit design
- CPU Architecture (W10–W11) — How gates build processors; FDE cycle
- GPU (W12–W13) — Parallel processing and modern applications
- Primary Memory (W13) — Memory hierarchy and cache behaviour
- Secondary Storage (W14) — Storage technologies and selection
- Compression (W14) — Data reduction techniques
- Cloud Computing (W15) — Service models and virtualization
Learning Objectives
By the end of this topic, you should be able to:
- Describe the 7 fundamental logic gates and construct truth tables for compound expressions (A1.2.3)
- Construct Karnaugh maps and apply Boolean algebra rules to simplify expressions (A1.2.4, A1.2.5)
- Describe CPU components (ALU, CU, registers) and explain the fetch-decode-execute cycle (A1.1.1, A1.1.5)
- Describe the GPU and its real-world applications; compare CPU and GPU architectures (HL) (A1.1.2, A1.1.3)
- Describe the memory hierarchy: registers, cache, RAM, ROM — and explain cache hit vs miss (A1.1.4)
- Describe secondary storage technologies and evaluate suitability for different scenarios (A1.1.7)
- Explain lossy vs lossless compression, RLE, and transform coding (A1.1.8)
- Describe cloud computing service models (SaaS, PaaS, IaaS) and virtualization concepts (A1.1.9, A1.3.2)
Connections
- Information Layer — Number systems and data representation (A1.2.1–A1.2.2) underpin how hardware stores and processes data
- Operating Systems Layer — OS manages hardware resources: memory management, process scheduling, virtualization (A1.3)
- Programming Layer — Understanding hardware helps explain performance characteristics: why arrays are fast, how cache affects loops, why sorting matters
- Communication Layer — Networking hardware connects to cloud computing and distributed systems (A2)