Primary Memory
IB Syllabus: A1.1.4 — Describe different types of primary memory
Table of Contents
- Key Concepts
- Worked Examples
- Quick Code Check
- Trace Exercise
- Spot the Error
- Fill in the Blanks
- Predict the Output
- Practice Exercises
- Connections
Key Concepts
Memory Hierarchy
Not all memory is created equal. Computers use a layered hierarchy that balances speed, size, and cost. Data moves between these layers as the CPU needs it.
┌─────────┐ Fastest, Smallest, Most Expensive
│Registers│
┌┴─────────┴┐
│ L1 Cache │
┌┴───────────┴┐
│ L2 Cache │
┌┴─────────────┴┐
│ L3 Cache │
┌┴───────────────┴┐
│ RAM │
┌┴─────────────────┴┐
│ Secondary Storage │ Slowest, Largest, Cheapest
└────────────────────┘
The key tradeoff: faster memory costs more per byte and is physically smaller. This is why computers do not simply use the fastest memory for everything.
RAM (Random Access Memory)
- Volatile — loses all contents when power is switched off
- Built from DRAM (Dynamic RAM) — stores each bit as a charge in a capacitor that must be constantly refreshed
- Stores running programs and the data they are actively working with
- “Random access” means any byte can be read in the same time, regardless of its address
- Typical capacity: 8-64 GB in modern computers
ROM (Read-Only Memory)
- Non-volatile — retains contents without power
- Contains BIOS/UEFI firmware — the first instructions the CPU runs on startup
- Cannot be easily modified (written to only once, or very rarely with special tools)
- Small capacity — just enough for boot instructions
- Every computer needs ROM so it knows how to start up before the OS is loaded from storage
Cache Memory
Cache sits between the CPU and RAM to speed up data access. It stores copies of frequently or recently used data so the CPU does not have to wait for the slower RAM.
- Built from SRAM (Static RAM) — uses flip-flop circuits, much faster than DRAM but far more expensive per bit
- Organised into levels, each with different speed and size characteristics:
| Level | Typical Size | Typical Access Time | Location |
|---|---|---|---|
| L1 Cache | 32-64 KB per core | ~1 ns | On the CPU core itself |
| L2 Cache | 256 KB - 1 MB | ~3-5 ns | Per-core or shared between two cores |
| L3 Cache | 4-32 MB | ~10-15 ns | Shared across all cores |
| RAM (comparison) | 8-64 GB | ~50-100 ns | Separate chip on motherboard |
The pattern is clear: each level further from the CPU is larger but slower.
Cache Hit vs Cache Miss
- Cache hit: the requested data IS found in the cache — the CPU gets it quickly
- Cache miss: the data is NOT in the cache — the CPU must fetch it from RAM (much slower)
- Hit rate: the percentage of memory accesses that are cache hits (higher is better; modern CPUs achieve 95%+ hit rates)
- Locality of reference explains why caches work so well:
- Temporal locality — data used recently is likely to be used again soon
- Spatial locality — data stored near recently accessed data is likely to be needed next
Registers
- The fastest memory in the entire system, located inside the CPU itself
- Hold the data and instructions currently being processed
- Very small capacity — each register holds a single value (typically 32 or 64 bits)
- Examples: Program Counter (PC), Memory Address Register (MAR), Memory Data Register (MDR), Instruction Register (IR), Accumulator (AC)
Virtual Memory
Virtual memory is not explicitly listed in A1.1.4 (2027 syllabus) but is commonly examined in IB CS and relates to A1.3.2 memory management. It is an important concept to understand.
- Uses secondary storage (SSD/HDD) as an extension of RAM when physical RAM is full
- Allows running programs larger than available RAM
- The OS divides memory into fixed-size pages and swaps them between RAM and disk as needed
- Thrashing occurs when the system spends more time swapping pages than executing programs — this severely degrades performance
- Adding more physical RAM is the most effective solution to thrashing
Enrichment: Boot Process
This goes beyond the IB syllabus but helps build understanding of why ROM matters.
- Power on — the CPU reads its first instructions from ROM (BIOS/UEFI)
- POST (Power-On Self Test) — hardware components are checked
- Bootloader — found on secondary storage, loaded into RAM
- OS loaded — the operating system is transferred from storage into RAM
- OS takes control — the system is ready for use
This is why ROM is essential: without it, the CPU would have no instructions to follow when the computer first turns on, and the OS (stored on secondary storage) could not be loaded.
Worked Examples
Example 1: Memory Hierarchy Comparison
| Criterion | Registers | Cache (L1) | RAM | Secondary Storage |
|---|---|---|---|---|
| Speed | Fastest (~0.5 ns) | Very fast (~1 ns) | Fast (~50-100 ns) | Slow (~0.1 ms SSD) |
| Capacity | Bytes | KB | GB | TB |
| Cost per GB | Highest | Very high | Moderate (~$3-5) | Low (~$0.05-0.10) |
| Volatile? | Yes | Yes | Yes | No |
| Example use | Holding the current instruction | Recently accessed variables | Running applications | Storing files and the OS |
Example 2: Cache Hit/Miss Scenario
A program accesses memory addresses in this order: 100, 104, 100, 200, 100.
Assume the cache starts empty. Each access either hits (data already cached) or misses (must fetch from RAM).
| Access # | Address | In cache? | Result | Cache contents after |
|---|---|---|---|---|
| 1 | 100 | No | Miss — fetch from RAM | {100} |
| 2 | 104 | No | Miss — fetch from RAM | {100, 104} |
| 3 | 100 | Yes | Hit — served from cache | {100, 104} |
| 4 | 200 | No | Miss — fetch from RAM | {100, 104, 200} |
| 5 | 100 | Yes | Hit — served from cache | {100, 104, 200} |
Hit rate = 2 hits out of 5 accesses = 40%. Access 3 and 5 demonstrate temporal locality — address 100 was reused.
Quick Code Check
Q1. Which type of primary memory is volatile and stores running programs?
Q2. What does cache memory store?
Q3. What happens during a cache miss?
Q4. Why is L1 cache faster than L3 cache?
Q5. What is stored in ROM?
Trace Exercise
A simple cache has 4 slots. When full, the oldest entry is replaced (FIFO). Track whether each memory request is a hit or miss.
| Slot 0 | Slot 1 | Slot 2 | Slot 3 |
|---|---|---|---|
| empty | empty | empty | empty |
Memory accesses in order: A, B, C, D, A, E, A, B
| Request # | Address | Hit / Miss | Slot 0 | Slot 1 | Slot 2 | Slot 3 |
|---|---|---|---|---|---|---|
| 1 | A | |||||
| 2 | B | |||||
| 3 | C | |||||
| 4 | D | |||||
| 5 | A | |||||
| 6 | E | |||||
| 7 | A | |||||
| 8 | B |
Total hits: out of 8 requests. Hit rate:
Request 5 is a hit because A is still in the cache. But request 7 is a miss — A was evicted at request 6 when E replaced the oldest entry (slot 0). This shows how a small cache with FIFO replacement can lose useful data.
Spot the Error
A student wrote this description of memory types. One line contains a factual error. Click the incorrect line, then pick the correction.
Pick the correct fix for line 3:
Fill in the Blanks
Complete the memory hierarchy description by filling in each blank.
Fill in the correct memory type or term for each statement:
is the fastest type of memory and is located inside the CPU.
memory is volatile and stores running programs.
memory is non-volatile and contains the boot firmware.
sits between the CPU and RAM to speed up data access.
When data is found in cache, it is called a cache .
Predict the Output
A cache has 4 slots and starts empty. The following memory accesses occur:
Access 1: Address X → miss (loaded into cache)
Access 2: Address Y → miss (loaded into cache)
Access 3: Address Z → miss (loaded into cache)
Access 4: Address X → ???Is access 4 a hit or a miss? Type your answer:
Practice Exercises
Core
-
Memory comparison table — Create a table comparing RAM, ROM, cache, and registers across five criteria: speed, capacity, volatility, cost per byte, and primary purpose.
-
Define with examples — Define cache hit and cache miss. For each, give a real-world analogy (e.g., finding a book on your desk vs going to the library).
-
RAM and ROM — Explain why a computer needs both RAM and ROM. What would happen if a computer had only RAM? What if it had only ROM?
Extension
-
Cache levels — Explain why L1 cache is faster but smaller than L3 cache. Why not make all cache L1-speed?
-
Virtual memory — Describe what happens when a computer runs out of physical RAM. Explain how virtual memory helps and what problem arises if it is used too heavily.
Challenge
-
System comparison — A gaming PC has 32 GB RAM and 32 MB L3 cache. A budget office PC has 8 GB RAM and 4 MB L3 cache. Evaluate which system is better suited for video editing, justifying your answer with reference to how video editing uses memory.
-
Thrashing analysis — A school server runs 50 virtual machines simultaneously. Users report the system has become extremely slow. Explain how thrashing could be the cause and propose two solutions, one hardware-based and one software-based.
Connections
- Prerequisites: CPU Architecture — registers are part of the CPU; the FDE cycle explains why fast memory access matters
- Related: Logic Gates — flip-flop circuits form the basis of SRAM used in cache
- Related: Secondary Storage — the next level down in the memory hierarchy
- Forward: Operating Systems Layer — the OS manages memory allocation, paging, and virtual memory (A1.3.2)